This is a template for calculating the component values for a passive loop filter like the ones used with most IC PLL circuits. Select a loop bandwidth, desired phase margin, Kpd, Kv, and N as shown below. This applies to passive loop filters driven by a charge pump phase detector and have the general block diagram form shown here.

1) Measure the tuning characteristics of the VCO and calculate Kv as shown.

Low frequency and corresponding tuning voltage

High frequency and corresponding tuning voltage

This is the VCO tuning rate constant.

Same as above but in angular form.

2) Determine the phase detector gain constant. This is from the manufacturer's data sheet information.

Minimum and maximum current from the phase detector.

Phase detector gain constant in angular form. Notice
these phase detectors have +/-360 degree range.

3) Select a loop bandwidth. 200Hz to 2000Hz is a good starting point for most fixed frequency applications using passive loop filters.

4) Select a reference frequency.

Note: This is the internal phase comparison frequency, not the external reference
oscillator frequency.

5) Calculate the division ratio. In this example the middle of the VCO frequency range is used as the output
frequency. This is divided by the reference frequency to give the division ratio.

6) Select an open loop phase margin. 45 degrees is a good value to start with and should work well.

The time constants can now be calculated and the circuit component values derived.

microsecond defined

This is the relationship of the components
in a typical passive loop filter circuit.

Here are the values for this design:

Now that the filter components have been selected, the PLL loop response can be checked.

Loop filter function

Open loop gain

Closed loop response

Open loop gain

Open loop phase response

Closed loop phase response

Additional reference spur suppression can be obtained with the third order loop filter. In this case, start by selecting the desired spur attenuation (say 20dB) and select a value for C3. C3 should be less than C1/10.

This is the third order filter configuration

The new loop bandwidth

Reduction in loop bandwidth
due to additional pole

Here are the new filter
circuit component values

In order to get a more precise prediction of the loop response, the phase detector sampling delay
must be considered.

Phase detector with sampling delay equation

Now that the filter components have been selected, the PLL the third-order loop response can be checked.

Loop filter equation

Open loop gain

Closed loop phase response

Here's what the third-order response looks like:

Open loop gain

Open loop phase response

Closed loop phase response

Prepared by Stuart Rumley
Valon Technology, LLC